1. Field of the Invention
This invention relates to the field of data processing. More particularly, this invention relates to data processing systems having asynchronous internal and external clocks.
2. Description of the Prior Art
It is known to provide microprocessors that use an internal clock with a high frequency for on-chip operations and an external clock with a lower frequency for off-chip operations. In this way, on-chip operations, such as arithmetic operations and cache accesses, can proceed at a higher speed than off-chip operations for which the use of relatively large external buses places a limiting factor upon the external clock speed.
One mechanism for improving the data processing performance of such systems is to provide a write buffer. The write buffer is used to store pending off-chip write requests (e.g. write accesses involving both a write address and write data) whilst maintaining the high speed operation at the internal clock frequency. The data in the write buffer is then written out to the main memory at a slower memory clock rate independently of the processor core. The processor core and write buffer effectively operate in parallel.
An important consideration in such operation is that the change between the internal clock frequency and the external clock frequency should be synchronised to avoid problems occurring, such as meta-stability which could otherwise occur if a request occurred right on a transition of the external clock. Synchronisation mechanism are provided to allow this meta-stability to settle before a write request at the external clock is generated.
In order to preserve the integrity of such data processing systems, it is important that write requests are serviced in the same order that they are issued, irrespective of whether they are buffered or unbuffered.
Another factor influencing such systems is the trend towards increasing clock frequencies. Advances in the design and fabrication technology of integrated circuit microprocessors have led to a steady increase in attainable clock frequencies. Whilst this allows more processing operations to be performed in a given time, it tends to give rise to problems in other areas, such as the time taken for accesses to external peripherals (e.g. memory) which have not advanced in clock speed so rapidly.